1. Field of the Invention
The invention relates to electronic data processing systems implemented in semiconductor integrated circuits and, more particularly, to integrated logic circuits employing MOS technology.
2. Description of the Related Art
Despite great effort expended to reduce the size and increase the speed of integrated circuit devices, the performance of such devices remains limited in certain aspects.
One well known technology used in the fabrication of integrated circuits is static complementary metal oxide semiconductor technology (CMOS). Static CMOS represents an advantageous design approach because it is stable between clock transitions. Accordingly, designing systems using static CMOS technology is relatively easy.
There are, however, important limitations associated with static CMOS logic circuits. One constraint of static CMOS is that each input must drive two transistors. A static CMOS design connects an output node to VDD through PMOS transistors, and the same output node to Ground through NMOS transistors. Every logic input connects to the gate of an NMOS transistor and to the gate of a PMOS transistor, switching one off as the other is switched on. In this way, the output node is switched between approximately ground potential and approximately VDD.
The result is highly deterministic, but each transistor contributes a capacitive load. Consequently, each input sees the capacitance of two gates as a load. It follows that the inputs of a static CMOS gate possess a larger RC time constant than would an input connected to a single comparable transistor gate. The result is that static CMOS is not as fast in operation as alternative technologies that require an input to drive only a single transistor.
In addition to its operating speed consequences, the presence of a second transistor for each gate means that static CMOS requires a relatively large amount of chip real estate. Also, static CMOS circuits require a relatively large number of interconnections, and thus wiring is more complex and requires additional layers of metalization.
Furthermore, static CMOS tends to exhibit relatively high transient power dissipation during switching. The reason for this is apparent from the structure of static CMOS logic, in which a PMOS transistor is operatively connected between a VDD rail and an output node. An NMOS transistor is operatively connected between the same output node and ground. In steady-state operation, one or the other of the NMOS and PMOS transistors is in a nonconductive state, while the other is conductive. Current through the conductive transistor is generally very small, since the typical output is loaded only with the leakage current flowing into the gates of other NMOS transistors.
During switching, however, the situation is different. Each NMOS and PMOS transistor must pass through a linear region during the time when it is switching between on and off states. Accordingly, since the NMOS and PMOS transistors of static CMOS are arranged to switch simultaneously, there is a period of time during which both are in linear operation. During this period, current flows directly from VDD through the PMOS transistor to the output node and from the output node through the NMOS transistor to ground. The product of this current and the voltage drop across the two transistors (VDD) constitutes transient power dissipation. Although brief, this transient is fairly large. The result is significant power dissipation, in those transistors, during switching.
Moreover, because PMOS transistor hole mobility is about three times lower than the mobility of electrons in an NMOS transistor of comparable size, CMOS switching transients are highly asymmetrical. The charge transient of the capacitive load in a static CMOS circuit takes far longer than the discharge transient of the same load. To compensate for this asymmetry, PMOS devices are often fabricated with increased area as compared NMOS devices in the same circuit. While this tends to improve the symmetry of switching transients, it incurs costs measured in additional stray capacitance, a larger RC time constant, and increased area requirements.
It is accordingly clear that, despite its benefits, static CMOS has several significant drawbacks. As a result, several alternative technologies to static CMOS have been developed. These include Monotonic CMOS, Pseudo-NMOS Static Logic, and Zipper Logic. Each of these has certain advantages, but also disadvantages.
Monotonic CMOS circuitry avoids some of the problems of traditional CMOS by limiting the set of allowed transitions so as to take advantage of the faster portions of the asymmetric CMOS switching transients. In Monotonic CMOS circuitry, the large charge-up time through the PMOS devices is effectively hidden by pre-charging the output node to VDD pursuant to a clock signal. When the clock signal is in a pre-charge state, a PMOS pre-charge transistor, receiving the clock signal at its gate, forms a conductive path between VDD and an output node of a Monotonic CMOS circuit. In this way the capacitance of the output node is pre-charged to VDD. When the clock transitions to an evaluation state, the pre-charge transistor is non-conductive, and a combination of PMOS and NMOS transistors, configured otherwise like static CMOS, controls the state of the output node. In like fashion, Monotonic CMOS may also include circuits that pre-charge an output node low. Accordingly, the outputs of a circuit are pre-charged high (for a pull-down gate) or low (for a pull-up gate), depending on the design of the circuit. Note that, during an evaluation period following the pre-charge period the gates behave monotonically; that is, the output state of the circuit either remains unchanged, or transitions in a single direction. For example the only possible output transitions for a pull-down monotonic gate are 1 to 1, or 1 to 0. This contrasts with regular static CMOS in which four transitions are possible; 0 to 0, 1 to 1, 0 to 1, or 1 to 0.
The pull-up and pull-down gates of conventional monotonic static CMOS are cascaded in alternating sequence. By appropriate logic optimization, a circuit can be developed that reduces operating time and power consumption. Each logic input, however, still drives two transistor gates. Thus Monotonic CMOS requires fairly large amounts of chip real estate and provides only a limited improvement over static CMOS in operating speed.
A further conventional approach is to prepare circuits using static pseudo-NMOS technology. Pseudo-NMOS technology differs from CMOS in that each input drives only a single transistor gate. This is achieved by using a PNMOS device as a load. This technology also has certain disadvantages, however. In particular, although wiring complexity is significantly reduced, in comparison to the above noted technologies, static DC power consumption is increased.
A further conventional approach to improving switching speed and gate loading is the use of zipper-CMOS logic circuits. In zipper-CMOS, sequentially alternating circuit portions of NMOS and CMOS employ clocked precharging portions of complementary technology. In zipper CMOS, logic evaluation networks of NMOS transistors connect output nodes to ground, whereas logic evaluation networks of PMOS transistors connect output nodes to VDD.
Although each of the foregoing technologies has desirable aspects, and is advantageously applied in certain circumstances, there exists a need for a family of logic circuits which achieves high speed and low power dissipation within reduced spatial confines.